In design and fabrication of systems, such as digital computers or communication/electronic apparatus, transmission lines associated with the systems may pose some concern. Signals transmitted through a transmission line may swing to a signal voltage deviating from a “high” or “low” level due to an unwanted effect, such as a signal reflection. The signal reflection may result from a mismatch between transmission line impedance and driver impedance and/or receiver impedance. A receiver that processes a signal may exhibit errors due to incorrect judgments made due to the signal reflection.
A termination may be used to enhance signal integrity and to increase operating bandwidth by reducing signal line reflection. FIG. 1 is a block diagram that illustrates a system 100 comprising a plurality of conventional termination devices 110a, 110b, 110c, 110d, and 110e (aggregately referred to as “devices 110”) each embedding an active termination circuit. Each of the devices 110 comprises a transmission driver 112, a receiving driver 114, and an active termination circuit 120. The transmission driver 112 is controlled by a driver enable signal DRIVER_ENABLE and transmits a transmission signal DRIVER_SIGNAL to a bus 102. The receiving driver 114 is controlled by a receiver enable signal RECEIVER_ENABLE and receives a received signal RECEIVED_SIGNAL from the bus 102. The active termination circuit 120 comprises a switch 122 that is coupled between a termination voltage VTERM and a trimmable termination resistor 124 and is controlled by a termination enable signal TERMINATION_ENABLE.
The active termination circuit 120 typically comprises a relatively simple termination circuit so as to accomplish a fast switch-on/off. The active termination circuit 120 may be in a termination enable state or a termination disable state. The termination resistor 124 is trimmed through a predetermined calibration process so as to provide an optimal termination for the bus 102.
In a memory device comprising an active termination circuit (e.g., an SDRAM), a termination resistor 124 is trimmed during a power-up process and an initialization process. Power-up and initialization operations of a conventional SDRAM are illustrated in FIG. 2. As shown in FIG. 2, after the power supply voltages (e.g., VDD and VDDQ) are applied and all input signals are maintained in a stable state for at least 200 μs, differential system clocks CK and CKB are input. A series of predetermined commands, such as, a precharge all banks command, an extended mode register set (EMRS) command for enabling a delay locked loop (DLL), an MRS command for resetting the DLL, a precharge all banks command, first and second auto refresh commands, and a command for initializing a mode register are performed on rising edges of the system clock CK. The termination resistor 124 in the active termination circuit 120 shown in FIG. 1 is trimmed by the EMRS command during the power-up and initialization process.
During the power-up and initialization process, the system clocks CK and CKB are typically input with the same frequency as an operation frequency of the SDRAM. For example, if the operation frequency of the SDRAM is 500 MHz, a clock cycle (tCC) is 2 ns. In a case where a setup/hold timing margin is reduced, the EMRS command applied at 500 MHz may be regarded as an invalid command. If operations of the EMRS command terminate due to the command being invalid before an operation for setting an active termination value is complete, then the termination resistor 124 may be set to an inappropriate value, which may result in signal reflection in signals transmitted on the bus 102. As a result, the SDRAM may be unable to recognize or may misinterpret its commands.